43 lines
828 B
Markdown
43 lines
828 B
Markdown
# verilog 环境
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### win
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```bash
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# Quartus
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# 参考 https://fpgasoftware.intel.com/static/quick_start_guide/quick_start_guide_21.1_zh-cn.pdf
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```
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### mac
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```bash
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git clone https://github.com/steveicarus/iverilog.git
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cd iverilog
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# yosys综合工具
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git clone https://github.com/YosysHQ/yosys.git
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cd yosys
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brew tap Homebrew/bundle && brew bundle
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make
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sudo make install
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# 显示电路图工具
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cd https://gitlab.com/graphviz/graphviz.git
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cd graphviz
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brew install automake libtool autoconf
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./autogen.sh
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./configure
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# 编译可能需要修改源码 我用的分支stable_release_2.44.0 改了两处 自己可以根据报错去看源码处理
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# 一处 lib/sfdpgen/PriorityQueue.c mollc.h 改为 #include <sys/malloc.h>
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# cmd/tools/graph_generator.h 添加 extern void makeTetrix(int, edgefn);
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make
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sudo make install
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```
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