verilog 环境

win

# Quartus
# 参考 https://fpgasoftware.intel.com/static/quick_start_guide/quick_start_guide_21.1_zh-cn.pdf

mac

git clone https://github.com/steveicarus/iverilog.git
cd iverilog

# yosys综合工具
git clone https://github.com/YosysHQ/yosys.git
cd yosys
brew tap Homebrew/bundle && brew bundle
make
sudo make install
# 显示电路图工具
cd https://gitlab.com/graphviz/graphviz.git
cd graphviz
brew install automake libtool autoconf
./autogen.sh
./configure
# 编译可能需要修改源码 我用的分支stable_release_2.44.0 改了两处 自己可以根据报错去看源码处理
# 一处 lib/sfdpgen/PriorityQueue.c  mollc.h 改为 #include <sys/malloc.h>
# cmd/tools/graph_generator.h 添加 extern void makeTetrix(int, edgefn);
make
sudo make install

828 B Raw Blame History

verilog 环境

win

mac

828 B

Raw Blame History