veypi/DigitalCalibration
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

update citations

Browse Source
This commit is contained in:
veypi 2021-11-09 00:59:39 +08:00
parent 302a0fcfbd
commit 22b8523368
1 changed files with 31 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
README.md
View File

@ -2,32 +2,50 @@
## target
### 研究意义
​ 模数转换器是各种数字系统中不可缺少的组成部分，其性能的优劣直接关系整体系统的性能和功能发挥，随着处理器和信号处理技术的不断发展，对adc的性能要求也越来越高，高速高精度已成为信号处理领域必要要求。但是，随着流水线ADC的精度提高的12bit以上时，工艺的偏差导致的电容失配、运放的非理想醒
### 研究现状分析
### 研究方案
1. 研究目标
2. 研究内容
3. 拟解决的问题
4. 拟采取的研究方法及可行性分析
### citations
[1]丁洋, 王宗民. 一种基于统计的流水线ADC数字后台校准方法[J]. 微电子学与计算机, 2011, 28(2):5.
[1]丁洋, 王宗民. 一种基于统计的流水线ADC数字后台校准方法[J]. 微电子学与计算机, 2011, 28(2):5. [>>>](https://public.veypi.com/research/digitalcalibration/citations/%E4%B8%80%E7%A7%8D%E5%9F%BA%E4%BA%8E%E7%BB%9F%E8%AE%A1%E7%9A%84%E6%B5%81%E6%B0%B4%E7%BA%BFADC%E6%95%B0%E5%AD%97%E5%90%8E%E5%8F%B0%E6%A0%A1%E5%87%86%E6%96%B9%E6%B3%95.pdf)
[1]郭静宜, 李冬梅, 刘力源,等. 一种适用于流水线ADC的数字校准算法的硬件实现[J]. 高技术通讯, 2009(03):290-294.
[1]郭静宜, 李冬梅, 刘力源,等. 一种适用于流水线ADC的数字校准算法的硬件实现[J]. 高技术通讯, 2009(03):290-294. [>>>](https://public.veypi.com/research/digitalcalibration/citations/%E4%B8%80%E7%A7%8D%E9%80%82%E7%94%A8%E4%BA%8E%E6%B5%81%E6%B0%B4%E7%BA%BFADC%E7%9A%84%E6%95%B0%E5%AD%97%E6%A0%A1%E5%87%86%E7%AE%97%E6%B3%95%E7%9A%84%E7%A1%AC%E4%BB%B6%E5%AE%9E%E7%8E%B0.pdf)
[1]吴俊杰, 朱从益, 刘海涛. 一种应用于流水线ADC数字校准算法及实现[J]. 现代雷达, 2014, 36(9):44-48.
[1]吴俊杰, 朱从益, 刘海涛. 一种应用于流水线ADC数字校准算法及实现[J]. 现代雷达, 2014, 36(9):44-48. [>>>](https://public.veypi.com/research/digitalcalibration/citations/%E4%B8%80%E7%A7%8D%E5%BA%94%E7%94%A8%E4%BA%8E%E6%B5%81%E6%B0%B4%E7%BA%BFADC%E6%95%B0%E5%AD%97%E6%A0%A1%E5%87%86%E7%AE%97%E6%B3%95%E5%8F%8A%E5%AE%9E%E7%8E%B0.pdf)
[1]戴澜, 周玉梅, 胡晓宇,等. 一种流水线ADC数字校准算法实现[J]. 半导体学报：英文版, 2008, 29(5):5.
[1]戴澜, 周玉梅, 胡晓宇,等. 一种流水线ADC数字校准算法实现[J]. 半导体学报：英文版, 2008, 29(5):5. [>>>](https://public.veypi.com/research/digitalcalibration/citations/%E4%B8%80%E7%A7%8D%E9%80%82%E7%94%A8%E4%BA%8E%E6%B5%81%E6%B0%B4%E7%BA%BFADC%E7%9A%84%E6%95%B0%E5%AD%97%E6%A0%A1%E5%87%86%E7%AE%97%E6%B3%95%E7%9A%84%E7%A1%AC%E4%BB%B6%E5%AE%9E%E7%8E%B0.pdf)
[1]张文莲. 折叠内插ADC中数字校准电路设计[J]. 电子制作, 2020(13):4.
[1]张文莲. 折叠内插ADC中数字校准电路设计[J]. 电子制作, 2020(13):4. [>>>](https://public.veypi.com/research/digitalcalibration/citations/%E6%8A%98%E5%8F%A0%E5%86%85%E6%8F%92ADC%E4%B8%AD%E6%95%B0%E5%AD%97%E6%A0%A1%E5%87%86%E7%94%B5%E8%B7%AF%E8%AE%BE%E8%AE%A1_%E5%BC%A0%E6%96%87%E8%8E%B2.pdf)
[1]杨一波. 时分交替ADC系统数字校准算法与FPGA实现[D]. 电子科技大学.
[1]杨一波. 时分交替ADC系统数字校准算法与FPGA实现[D]. 电子科技大学. [>>>](https://public.veypi.com/research/digitalcalibration/citations/%E6%97%B6%E5%88%86%E4%BA%A4%E6%9B%BFADC%E7%B3%BB%E7%BB%9F%E6%95%B0%E5%AD%97%E6%A0%A1%E5%87%86%E7%AE%97%E6%B3%95%E4%B8%8EFPGA%E5%AE%9E%E7%8E%B0.pdf)
[1] Fukazawa M , Oshima T , Fujiwara M , et al. A CT 2-2 MASH Δ Σ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction[J]. IEEE Journal of Solid-State Circuits, 2021, PP(99):1-1.
[1] Fukazawa M , Oshima T , Fujiwara M , et al. A CT 2-2 MASH Δ Σ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction[J]. IEEE Journal of Solid-State Circuits, 2021, PP(99):1-1. [>>>](https://public.veypi.com/research/digitalcalibration/citations/A%20CT%202-2%20MASH%20--%20ADC%20With%20Multi-Rate%20LMS-Based%20Background%20Calibration%20and%20Input-Insensitive%20Quantization-Error%20Extraction.pdf)
[1]Moon, Un-Ko, Bang-Sup, et al. Background digital calibration techniques for pipelined ADC's.[J]. IEEE Transactions on Circuits & Systems Part II: Analog & Digital Signal Processing, 1997, 44(2):102-102.
[1]Moon, Un-Ko, Bang-Sup, et al. Background digital calibration techniques for pipelined ADC's.[J]. IEEE Transactions on Circuits & Systems Part II: Analog & Digital Signal Processing, 1997, 44(2):102-102. [>>>](https://public.veypi.com/research/digitalcalibration/citations/Background%20Digital%20Calibration%20Techniques%20for%20Pipelined%20ADC%E2%80%99s.pdf)
[1] Wei L , Tao W , Temes G C . Digital foreground calibration methods for SAR ADCs[C]// IEEE. IEEE, 2012.
[1] Wei L , Tao W , Temes G C . Digital foreground calibration methods for SAR ADCs[C]// IEEE. IEEE, 2012. [>>>](https://public.veypi.com/research/digitalcalibration/citations/Digital%20Foreground%20Calibration%20Methods%20for%20SAR%20ADCs%20.pdf)
[1]Grace, C. R , Hurst, et al. A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration[J]. Solid-State Circuits, IEEE Journal of, 2005, 40(5):1038-1046.
[1]Grace, C. R , Hurst, et al. A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration[J]. Solid-State Circuits, IEEE Journal of, 2005, 40(5):1038-1046. [>>>](https://public.veypi.com/research/digitalcalibration/citations/A%2012-bit%2080-Msample%3As%20Pipelined%20ADC%20with%20Bootstrapped%20Digital%20Calibration.pdf)
[1] Lee Z M , Wang C Y , Wu J T . A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration[J]. IEEE Journal of Solid-State Circuits, 2007, 42(10):2149-2160.
[1] Lee Z M , Wang C Y , Wu J T . A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital Background Calibration[J]. IEEE Journal of Solid-State Circuits, 2007, 42(10):2149-2160. [>>>](https://public.veypi.com/research/digitalcalibration/citations/a%20cmos%2015-bit%20125-ms%3As%20Time-Interleaved%20ADC%20with%20Digital%20Background%20Calibration.pdf)
[1] Shu Y S . Background digital calibration techniques for high-speed, high resolution analog-to-digital data converters[J]. Dissertations & Theses, 2008. [>>>](https://public.veypi.com/research/digitalcalibration/citations/Background%20digital%20calibration%20techniques%20for%20high-speed%2C%20high%20resolution%20analog-to-digital%20data%20converters.pdf)
[1] [数据转换器学习与设计](https://www.zhihu.com/column/c_1308071540374753280)
[1] Shu Y S . Background digital calibration techniques for high-speed, high resolution analog-to-digital data converters[J]. Dissertations & Theses, 2008.